Importance

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Abstract

Provided are a semiconductor memory device having a source synchronous interface capable of reducing jitter while minimizing overhead and a clocking method thereof. The semiconductor memory device comprises a phase locked loop (PLL) circuit receiving a first external clock signal for a command and address signal and generating a first internal clock signal, a first delay locked loop (DLL) circuit receiving a second external clock signal for predetermined bits of data and the first internal clock signal and generating a second internal clock signal locked to the second external clock signal, and a second DLL circuit receiving a third external clock signal for the remaining bits of the data and the first internal clock signal and generating a third internal clock signal locked to the third external clock signal.

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First Claim