Self aligning state machine
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United States of America Patent
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-
May 4, 2010
Grant Date -
N/A
app pub date -
Feb 14, 2007
filing date -
Feb 14, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.
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