Method, system, and computer program product for timing closure in electronic designs

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7721237
APP PUB NO 20080163148A1
SERIAL NO

11866376

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Abstract

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Disclosed is a method, system, and computer program product for timing closure with concurrent models for fabrication, metrology, lithography, and/or imaging processing analyses for electronic designs. Some embodiments of the present invention disclose a method for timing closure with concurrent process model analysis which comprises the act of generating a design for the one or more interconnect levels; analyzing the effects of the concurrent models to predict feature dimension variations based upon the concurrent models; modifying the design files to reflect the variations; determining one or more parameters based upon the concurrent models; and determining the impact of concurrent models upon the electrical and timing performance. Some embodiments disclose a computerized system for implementing the method(s) disclosed herein. Some embodiments also disclosed a computer program product comprising executable code for the method(s) disclosed herein.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Scheffer, Louis K Campbell, US 39 1245
White, David San Jose, US 206 7185

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