Method, system, and computer program product for timing closure in electronic designs
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United States of America Patent
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May 18, 2010
Grant Date -
Jul 3, 2008
app pub date -
Oct 2, 2007
filing date -
Dec 29, 2006
priority date (Note) -
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Abstract
Disclosed is a method, system, and computer program product for timing closure with concurrent models for fabrication, metrology, lithography, and/or imaging processing analyses for electronic designs. Some embodiments of the present invention disclose a method for timing closure with concurrent process model analysis which comprises the act of generating a design for the one or more interconnect levels; analyzing the effects of the concurrent models to predict feature dimension variations based upon the concurrent models; modifying the design files to reflect the variations; determining one or more parameters based upon the concurrent models; and determining the impact of concurrent models upon the electrical and timing performance. Some embodiments disclose a computerized system for implementing the method(s) disclosed herein. Some embodiments also disclosed a computer program product comprising executable code for the method(s) disclosed herein.
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- 15 United States
- 10 France
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- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 2655 SEELY AVENUE SAN JOSE CA 95134 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Scheffer, Louis K | Campbell, US | 39 | 1245 |
| White, David | San Jose, US | 206 | 7185 |
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| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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