Processor having a compare extension of an instruction set architecture
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United States of America Patent
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May 25, 2010
Grant Date -
Jan 24, 2008
app pub date -
Jun 4, 2007
filing date -
Jul 30, 1999
priority date (Note) -
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Abstract
A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.
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