Memory array structure and single instruction multiple data processor including the same and methods thereof
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United States of America Patent
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May 25, 2010
Grant Date -
May 15, 2008
app pub date -
Jun 1, 2007
filing date -
Nov 15, 2006
priority date (Note) -
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Abstract
A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.
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