Method for radiation tolerance by implant well notching

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United States of America Patent

PATENT NO 7725870
APP PUB NO 20090045841A1
SERIAL NO

11838286

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Abstract

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A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONNEW ORCHARD ROAD ARMONK NY 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beckenbaugh, Mark R Rochester, US 7 28
KleinOsowski, AJ Austin, US 16 203
Lukes, Eric J Stewartville, US 11 30

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