US Patent No: 7,737,003

Number of patents in Portfolio can not be more than 2000

Method and structure for optimizing yield of 3-D chip manufacture

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ALSO PUBLISHED AS: 20070080448
ATTORNEY / AGENT: (SPONSORED)
 

Importance

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Abstract

The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK, NY68180

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
DeMulder, Edward M Essex Junction, VT 4 5
Knickerbocker, Sarah H Hopewell Junction, NY 36 229
Shapiro, Michael J Austini, TX 37 86
Young, Albert M Fishkill, NY 44 181

Cited Art

Patent Info (Count) # Cites Year
 
SANDISK 3D LLC (5)
6,881,994 Monolithic three dimensional array of charge storage devices containing a planarized surface 145 2001
6,888,750 Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication 239 2001
6,593,624 Thin film transistors with vertically offset drain regions 54 2001
6,841,813 TFT mask ROM and method for making same 33 2001
6,737,675 High density 3D rail stack arrays 50 2002
 
INTEL CORPORATION (4)
6,661,085 Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack 45 2002
6,887,769 Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same 28 2002
6,645,832 Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack 20 2002
6,762,076 Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices 63 2002
 
TEXAS INSTRUMENTS INCORPORATED (3)
5,909,559 Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width 188 1997
6,105,119 Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems 91 1997
6,179,489 Devices, methods, systems and software products for coordination of computer main microprocessor and second microprocessor coupled thereto 80 1997
 
FREESCALE SEMICONDUCTOR, INC. (2)
5,927,993 Backside processing method 26 1992
2007/0023,121 Fabrication of three dimensional integrated circuit employing multiple die panels 27 2005
 
NVIDIA CORPORATION (1)
6,130,674 Dynamically selectable texture filter for computer graphics 7 1997
 
ROHM CO., LTD. (1)
6,724,084 Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device 26 2000
 
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA (1)
5,834,162 Process for 3D chip stacking 70 1996

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