Method and structure for optimizing yield of 3-D chip manufacture

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7737003
APP PUB NO 20070080448A1
SERIAL NO

11163226

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK, NY44931

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
DeMulder, Edward M Essex Junction, US 2 56
Knickerbocker, Sarah H Hopewell Junction, US 36 335
Shapiro, Michael J Austin, US 36 282
Young, Albert M Fishkill, US 35 439

Cited Art Landscape

Patent Info (Count) # Cites Year
 
SANDISK TECHNOLOGIES LLC (5)
6881994 Monolithic three dimensional array of charge storage devices containing a planarized surface 240 2001
6888750 Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication 294 2001
6593624 Thin film transistors with vertically offset drain regions 74 2001
6841813 TFT mask ROM and method for making same 108 2001
6737675 High density 3D rail stack arrays 72 2002
 
REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE (1)
5834162 Process for 3D chip stacking 84 1996
 
INTEL CORPORATION (4)
6661085 Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack 228 2002
6887769 Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same 164 2002
6645832 Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack 39 2002
6762076 Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices 260 2002
 
FREESCALE SEMICONDUCTOR, INC. (1)
* 5927993 Backside processing method 27 1992
 
ROHM CO., LTD. (1)
* 6724084 Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device 32 2000
 
TEXAS INSTRUMENTS INCORPORATED (3)
5909559 Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width 291 1997
6105119 Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems 127 1997
6179489 Devices, methods, systems and software products for coordination of computer main microprocessor and second microprocessor coupled thereto 118 1997
 
NVIDIA CORPORATION (1)
6130674 Dynamically selectable texture filter for computer graphics 8 1997
 
NXP USA, INC. (1)
* 2007/0023,121 Fabrication of three dimensional integrated circuit employing multiple die panels 45 2005
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
ELPIDA MEMORY, INC. (1)
* 2008/0009,124 Method of forming a semiconductor device 2 2007
 
INVENSAS CORPORATION (2)
* 9330954 Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof 1 2013
9559061 Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof 0 2016
* Cited By Examiner

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