Digital phase locked loop
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United States of America Patent
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Jun 15, 2010
Grant Date -
Dec 13, 2007
app pub date -
Aug 20, 2007
filing date -
Aug 16, 2001
priority date (Note) -
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Abstract
Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.
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