Fast hardware co-simulation reset using partial bitstreams
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United States of America Patent
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Jun 15, 2010
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app pub date -
Jan 31, 2006
filing date -
Jan 31, 2006
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Abstract
A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.
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