Method of visualization in processor based emulation system

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7739093
APP PUB NO 20050267732A1
SERIAL NO

11047802

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Abstract

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A processor-based emulation system for emulating an integrated circuit design, the processor-based emulation system including emulation circuitry and capture circuitry. The capture circuitry is operable to capture processing results from the emulation circuitry. The captured processing results can be used to identify functional errors in the integrated circuit design. Because the processor-based emulation system includes capture circuitry, emulation circuitry is not used for capturing the processing results.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CADENCE DESIGN SYSTEMS, INC.SAN JOSE, CA1694

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beausoleil, William F Hopewell Jct, US 28 770
Elmufdi, Beshara Sunnyvale, US 9 20
Sarkisian, Arthur P Tillson, US 1 11
Thomas, Lawrence A W. Hurley, US 7 33

Cited Art Landscape

Patent Info (Count) # Cites Year
 
MENTOR GRAPHICS (HOLDING) LTD. (8)
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5754827 Method and apparatus for performing fully visible tracing of an emulation 115 1995
5777489 Field programmable gate array with integrated debugging facilities 66 1995
5790832 Method and apparatus for tracing any node of an emulation 32 1996
5907697 Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network 21 1996
6057706 Field programmable gate array with integrated debugging facilities 29 1997
5999725 Method and apparatus tracing any node of an emulation 70 1998
6240376 Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging 47 1998
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
* 6173425 Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams 28 1998
 
CADENCE DESIGN SYSTEMS, INC. (26)
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5452239 Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system 276 1993
5680583 Method and apparatus for a trace buffer in an emulation system 88 1994
5551013 Multiprocessor for hardware emulation 339 1994
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5661662 Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation 72 1995
5644515 Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation 39 1995
5761488 Logic translation method for increasing simulation emulation efficiency 5 1996
5822564 Checkpointing in an emulation system 28 1996
5841967 Method and apparatus for design verification using emulation and simulation 81 1996
5946472 Apparatus and method for performing behavioral modeling in hardware emulation and simulation environments 49 1996
5920712 Emulation system having multiple emulator clock cycles per emulated clock cycle 65 1996
5963736 Software reconfigurable target I/O in a circuit emulation system 15 1997
6141636 Logic analysis subsystem in a time-sliced emulator 17 1997
5884066 Method and apparatus for a trace buffer in an emulation system 19 1997
5943490 Distributed logic analyzer for use in a hardware logic emulation system 72 1997
* 5970240 Method and apparatus for configurable memory emulation 60 1997
6035117 Tightly coupled emulation processors 31 1998
6051030 Emulation module having planar array organization 38 1998
6058492 Method and apparatus for design verification using emulation and simulation 48 1998
6523155 Method for partitioning a netlist into multiple clock domains 20 1998
6618698 Clustered processors in an emulation engine 58 1999
6832185 Non-synchronous hardware emulator 16 2000
6782355 Apparatus for improving concurrent behavior modeling with emulation 9 2000
6446249 Emulation circuit with a hold time algorithm, logic and analyzer and shadow memory 73 2000
6539535 Programmable logic device having integrated probing structures 47 2001
 
MENTOR GRAPHICS CORPORATION (3)
6061511 Reconstruction engine for a hardware circuit emulator 100 1998
6223148 Logic analysis system for logic emulation systems 33 1998
2001/0010,036 Logic analysis system for logic emulation systems 6 2001
 
FREESCALE SEMICONDUCTOR, INC. (1)
5784427 Feedback and shift unit 10 1996
 
SAMSUNG ELECTRONICS CO., LTD. (1)
* 6457141 Semiconductor device with embedded memory cells 28 1999
 
PIE DESIGNS SYSTEMS, INC. (1)
5425036 Method and apparatus for debugging reconfigurable emulation systems 275 1992
 
ARKOS, INC. (1)
5923865 Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing 11 1995
 
QUICKTURN DESIGN SYSTEMS, INC. (3)
4914612 Massively distributed simulation engine 81 1988
5109353 Apparatus for emulation of electronic hardware system 193 1988
5036473 Method of using electronically reconfigurable logic circuits 301 1989
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (8)
* 7904288 Hardware emulator having a variable input emulation group 4 2006
9015026 System and method incorporating an arithmetic logic unit for emulation 1 2010
8898051 System and method for implementing a trace interface 1 2010
* 2010/0318,338 System and Method For Implementing A Trace Interface 0 2010
* 2010/0318,952 System and Method Incorporating An Arithmetic Logic Unit For Emulation 0 2010
* 9372947 Compacting trace data generated by emulation processors during emulation of a circuit design 0 2014
9292639 Method and system for providing additional look-up tables 0 2014
9379846 System and method of encoding in a serializer/deserializer 0 2014
* Cited By Examiner

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