US Patent No: 7,739,093

Number of patents in Portfolio can not be more than 2000

Method of visualization in processor based emulation system

ALSO PUBLISHED AS: 20050267732

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Abstract

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A processor-based emulation system for emulating an integrated circuit design, the processor-based emulation system including emulation circuitry and capture circuitry. The capture circuitry is operable to capture processing results from the emulation circuitry. The captured processing results can be used to identify functional errors in the integrated circuit design. Because the processor-based emulation system includes capture circuitry, emulation circuitry is not used for capturing the processing results.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CADENCE DESIGN SYSTEMS, INC.SAN JOSE, CA1540

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beausoleil, William F Hopewell Junction, NY 37 525
Elmufdi, Beshara Sunnyvale, CA 7 9
Sarkisian, Arthur P Tillson, NY 2 4
Thomas, Lawrence A West Hurley, NY 8 21

Cited Art Landscape

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (26)
5,475,830 Structure and method for providing a reconfigurable emulation circuit without hold time violations 94 1992
5,452,239 Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system 249 1993
5,680,583 Method and apparatus for a trace buffer in an emulation system 75 1994
5,551,013 Multiprocessor for hardware emulation 169 1994
5,448,496 Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system 107 1994
5,661,662 Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation 67 1995
5,644,515 Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation 39 1995
5,761,488 Logic translation method for increasing simulation emulation efficiency 5 1996
5,822,564 Checkpointing in an emulation system 26 1996
5,841,967 Method and apparatus for design verification using emulation and simulation 74 1996
5,946,472 Apparatus and method for performing behavioral modeling in hardware emulation and simulation environments 44 1996
5,920,712 Emulation system having multiple emulator clock cycles per emulated clock cycle 52 1996
5,963,736 Software reconfigurable target I/O in a circuit emulation system 13 1997
6,141,636 Logic analysis subsystem in a time-sliced emulator 16 1997
5,884,066 Method and apparatus for a trace buffer in an emulation system 18 1997
5,943,490 Distributed logic analyzer for use in a hardware logic emulation system 67 1997
5,970,240 Method and apparatus for configurable memory emulation 50 1997
6,035,117 Tightly coupled emulation processors 24 1998
6,051,030 Emulation module having planar array organization 31 1998
6,058,492 Method and apparatus for design verification using emulation and simulation 41 1998
6,523,155 Method for partitioning a netlist into multiple clock domains 19 1998
6,618,698 Clustered processors in an emulation engine 41 1999
6,832,185 Non-synchronous hardware emulator 13 2000
6,782,355 Apparatus for improving concurrent behavior modeling with emulation 9 2000
6,446,249 Emulation circuit with a hold time algorithm, logic and analyzer and shadow memory 61 2000
6,539,535 Programmable logic device having integrated probing structures 36 2001
 
MENTOR GRAPHICS (HOLDING) LTD. (8)
5,574,388 Emulation system having a scalable multi-level multi-stage programmable interconnect network 64 1995
5,754,827 Method and apparatus for performing fully visible tracing of an emulation 105 1995
5,777,489 Field programmable gate array with integrated debugging facilities 65 1995
5,790,832 Method and apparatus for tracing any node of an emulation 30 1996
5,907,697 Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network 21 1996
6,057,706 Field programmable gate array with integrated debugging facilities 29 1997
5,999,725 Method and apparatus tracing any node of an emulation 66 1998
6,240,376 Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging 40 1998
 
MENTOR GRAPHICS CORPORATION (3)
6,061,511 Reconstruction engine for a hardware circuit emulator 82 1998
6,223,148 Logic analysis system for logic emulation systems 32 1998
2001/0010,036 Logic analysis system for logic emulation systems 4 2001
 
QUICKTURN DESIGN SYSTEMS, INC. (3)
4,914,612 Massively distributed simulation engine 80 1988
5,109,353 Apparatus for emulation of electronic hardware system 182 1988
5,036,473 Method of using electronically reconfigurable logic circuits 269 1989
 
ARKOS, INC. (1)
5,923,865 Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing 11 1995
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,784,427 Feedback and shift unit 8 1996
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
6,173,425 Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams 25 1998
 
PIE DESIGNS SYSTEMS, INC. (1)
5,425,036 Method and apparatus for debugging reconfigurable emulation systems 245 1992
 
SAMSUNG ELECTRONICS CO., LTD. (1)
6,457,141 Semiconductor device with embedded memory cells 25 1999

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (1)
7,904,288 Hardware emulator having a variable input emulation group 2 2006

Maintenance Fees

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7.5 Year Payment $3600.00 $1800.00 $900.00 Dec 15, 2017
11.5 Year Payment $7400.00 $3700.00 $1850.00 Dec 15, 2021
Fee Large entity fee small entity fee micro entity fee
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00

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