Leadframe and mold compound interlock in packaged semiconductor device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 22, 2010
Grant Date -
Apr 24, 2008
app pub date -
Oct 18, 2007
filing date -
Oct 18, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully