US Patent No: 7,746,101

Number of patents in Portfolio can not be more than 2000

Cascading input structure for logic blocks in integrated circuits

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Abstract

A cascading input structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes a plurality of substantially similar logic blocks arrayed to form a column of the logic blocks, and a self-timed vertical cascade chain. Each of the logic blocks has self-timed first and second inputs. The vertical cascade chain has a plurality of self-timed outputs, each of the self-timed outputs being coupled to a first self-timed input of a corresponding logic block in the column. In some embodiments, each logic block includes a multiply block having first and second self-timed inputs, where each output of the vertical cascade chain is coupled to the first input of the multiply block in the corresponding logic block. In some embodiments having a multiply block in the logic block, the inputs and output may not be self-timed.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
XILINX, INC.SAN JOSE, CA3059

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Young, Steven P Boulder, CO 202 4137

Cited Art

Patent Info (Count) # Cites Year
 
XILINX, INC. (23)
6,150,838 FPGA configurable logic block with multi-purpose logic/memory circuit 226 1999
6,184,712 FPGA configurable logic block with multi-purpose logic/memory circuit 40 1999
6,208,163 FPGA configurable logic block with multi-purpose logic/memory circuit 49 1999
2005/0144,210 Programmable logic device with dynamic DSP architecture 63 2004
7,467,175 Programmable logic device with pipelined DSP slices 29 2004
7,467,177 Mathematical circuit with dynamic rounding 28 2004
7,472,155 Programmable logic device with cascading DSP slices 47 2004
7,480,690 Arithmetic circuit with multiplexed addend inputs 29 2004
7,196,543 Integrated circuit having a programmable input structure with optional fanout capability 20 2005
7,202,698 Integrated circuit having a programmable input structure with bounce capability 26 2005
7,375,552 Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure 9 2005
7,274,211 Structures and methods for implementing ternary adders/subtractors in programmable logic devices 15 2006
2006/0190,516 Digital signal processing element having an arithmetic logic unit 31 2006
2006/0195,496 Digital signal processing circuit having a pattern detector circuit 31 2006
2006/0206,557 Arithmetic logic unit circuit 30 2006
2006/0212,499 Digital signal processing block having a wide multiplexer 30 2006
2006/0230,092 Architectural floorplan for a digital signal processing circuit 30 2006
2006/0230,093 Digital signal processing circuit having a pattern detector circuit for convergent rounding 30 2006
2006/0230,094 Digital signal processing circuit having input register blocks 64 2006
2006/0230,095 Digital signal processing circuit having a pre-adder circuit 30 2006
2006/0230,096 Digital signal processing circuit having an adder circuit with carry-outs 63 2006
2006/0288,069 Digital signal processing circuit having a SIMD circuit 30 2006
2006/0288,070 Digital signal processing circuit having a pattern circuit for determining termination conditions 33 2006
 
ACHRONIX SEMICONDUCTOR CORPORATION (4)
2008/0168,407 Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric 28 2007
2007/0256,038 SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS 37 2007
7,504,851 Fault tolerant asynchronous circuits 27 2007
7,505,304 Fault tolerant asynchronous circuits 26 2007
 
THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK (4)
6,850,092 Low latency FIFO circuits for mixed asynchronous and synchronous systems 21 2001
6,590,424 High-throughput asynchronous dynamic pipelines 32 2001
6,958,627 Asynchronous pipeline with latch controllers 45 2001
7,053,665 Circuits and methods for high-capacity asynchronous pipeline processing 11 2005
 
ALTERA CORPORATION (3)
2005/0127,944 Versatile logic element and logic array block 20 2005
7,538,579 Omnibus logic element 11 2006
2007/0252,617 VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK 11 2007
 
NIPPON TELEGRAPH AND TELEPHONE CORPORATION (3)
6,140,836 Self-timed pipelined datapath system and asynchronous signal control circuit 33 1998
6,225,827 Dynamic logic circuit and self-timed pipelined datapath system 25 1998
6,320,418 Self-timed pipelined datapath system and asynchronous signal control circuit 29 2000
 
CALIFORNIA INSTITUTE OF TECHNOLOGY (2)
5,999,961 Parallel prefix operations in asynchronous processors 11 1997
6,949,954 Method and apparatus for an asynchronous pulse logic circuit 14 2003
 
INTEL CORPORATION (2)
6,531,897 Global clock self-timed circuit with self-terminating precharge for high frequency applications 11 2000
7,050,324 Asynchronous static random access memory 17 2004
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
6,522,170 Self-timed CMOS static logic circuit 24 1998
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SUN MICROSYSTEMS, INC. (2)
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TABULA, INC. (2)
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7,652,498 Integrated circuit with delay selecting input selection circuitry 21 2007
 
UNIVERSITY OF WASHINGTON (2)
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CORNELL RESEARCH FOUNDATION, INC. (1)
7,157,934 Programmable asynchronous pipeline arrays 45 2004
 
CSWITCH CORPORATION (1)
7,417,456 Dedicated logic cells employing sequential logic and control logic functions 11 2006
 
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE (1)
2007/0126,474 Crossbar switch architecture for multi-processor SoC platform 9 2006
 
FUJITSU LIMITED (1)
5,513,132 Zero latency overhead self-timed iterative logic structure and method 17 1993
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
5,126,975 Integrated cache SRAM memory having synchronous write and burst read 93 1990
 
LSI LOGIC CORPORATION (1)
7,308,627 Self-timed reliability and yield vehicle with gated data and clock 6 2004
 
RICHTER, THOMAS, MR. (1)
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SAMSUNG ELECTRONICS CO., LTD. (1)
6,708,193 Linear summation multiplier array implementation for both signed and unsigned multiplication 16 2000
 
STMICROELECTRONICS S.A. (1)
6,476,643 Asynchronous circuit for detecting and correcting soft error and implementation method thereof 31 2001
 
STMICROELECTRONICS, INC. (1)
6,959,315 Self-timed digital processing circuits 7 2001
 
WARPSPEED CHIPS, LLC (1)
7,352,204 Automatic skew correction for differential signals 10 2006
 
WAVE SEMICONDUCTOR, INC. (1)
6,308,229 System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic 29 2000
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
2009/0289,660 INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES 8 2009

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
XILINX, INC. (3)
8,358,148 Programmable integrated circuit and method of asynchronously routing data in an integrated circuit 0 2010
8,294,490 Integrated circuit and method of asynchronously routing data in an integrated circuit 0 2010
8,402,164 Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit 0 2010

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