Microelectronic assemblies having compliancy and methods therefor

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7749886
APP PUB NO 20080150121A1
SERIAL NO

11643021

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.

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Patent Owner(s)

Patent OwnerAddress
ADEIA SEMICONDUCTOR SOLUTIONS LLC3025 ORCHARD PARKWAY SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gao, Guilian San Jose, US 146 4700
Haba, Belgacem Saratoga, US 769 23924
Oganesian, Vage Palo Alto, US 149 6013
Ovrutsky, David Ashkelon, IL 40 2056

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