NAND memory device and programming methods
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United States of America Patent
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Jul 6, 2010
Grant Date -
Mar 1, 2007
app pub date -
Aug 30, 2005
filing date -
Aug 30, 2005
priority date (Note) -
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Abstract
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.
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