Method and apparatus for gigabit packet assignment for multithreaded packet processing

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7751402
APP PUB NO 20040071152A1
SERIAL NO

10684078

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads—one for header segment processing and the other for handling payload segment(s)—or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA29065

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adiletta, Matthew J Worc, US 120 2985
Bernstein, Debra Sudbury, US 85 2742
Hooper, Donald F Shrewsbury, US 66 3476
Wolrich, Gilbert Framingham, US 131 3712

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NEC CORPORATION (4)
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MICROSOFT TECHNOLOGY LICENSING, LLC (3)
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AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (5)
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* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
* 2011/0083,000 DATA PROCESSING ARCHITECTURES FOR PACKET HANDLING 17 2010
 
RPX CLEARINGHOUSE LLC (3)
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* 2004/0141,462 Multi-staged services policing 14 2003
* 2011/0242,981 MULTI-STAGED SERVICES POLICING 3 2011
 
INTEL CORPORATION (5)
9128818 Memory mapping in a processor having multiple programmable units 0 2014
9830284 Memory mapping in a processor having multiple programmable units 0 2015
9830285 Memory mapping in a processor having multiple programmable units 0 2015
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9824038 Memory mapping in a processor having multiple programmable units 0 2015
 
XMOS LIMITED (2)
* 8219789 Interface processor 0 2007
* 2008/0229,311 Interface processor 1 2007
 
RAMBUS INC. (3)
8200686 Lookup engine 5 2005
* 2005/0243,827 Lookup engine 4 2005
* 8127112 SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream 9 2010
 
FUJITSU LIMITED (2)
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* 2010/0100,686 Cache controller and control method 1 2009
 
ORACLE AMERICA, INC. (1)
* 8195921 Method and apparatus for decoding multithreaded instructions of a microprocessor 0 2008
* Cited By Examiner

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