Method and apparatus for gigabit packet assignment for multithreaded packet processing

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United States of America Patent

PATENT NO 7751402
APP PUB NO 20040071152A1
SERIAL NO

10684078

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Abstract

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A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads—one for header segment processing and the other for handling payload segment(s)—or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA29065

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adiletta, Matthew J Worc, US 122 3006
Bernstein, Debra Sudbury, US 86 2752
Hooper, Donald F Shrewsbury, US 66 3494
Wolrich, Gilbert Framingham, US 131 3734

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