Video encoding and video/audio/data multiplexing device
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United States of America Patent
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Jul 6, 2010
Grant Date -
Sep 4, 2008
app pub date -
May 13, 2008
filing date -
Apr 6, 1999
priority date (Note) -
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Abstract
The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.
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