Configuration layout number controlled adjustable delaying of connection path changes among processors in array to reduce transition glitches
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United States of America Patent
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Jul 6, 2010
Grant Date -
Aug 14, 2008
app pub date -
Feb 13, 2008
filing date -
Feb 14, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.
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