Multiple thread in-order issue in-order completion DSP and micro-controller
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United States of America Patent
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Jul 20, 2010
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N/A
app pub date -
Sep 6, 2007
filing date -
Dec 3, 2003
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Abstract
An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage. The various stages are provided a thread ID such that alternating stages use a first thread ID, and the other stages use a second thread ID. Each stage which requires access to thread ID specific context information uses the thread ID to specify this context information.
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