Methods and apparatus for structure layout optimization for multi-threaded programs

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United States of America Patent

PATENT NO 7765242
APP PUB NO 20080282035A1
SERIAL NO

11801970

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Abstract

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A computer-implemented method for performing structure layout optimization of a data structure in a multi-threaded environment is provided. The method includes determining a set of code concurrency values. The method also includes calculating a set of cycle gain values. The method further includes employing the set of cycle gain values and the set of code concurrency values to create a field layout graph, which is configured to illustrate relationship between a set of data fields of the data structure. The method yet also includes employing a cluster algorithm to the field layout graph to create a set of clusters. Each cluster of the set of clusters is employed to generate a cache line.

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Patent Owner(s)

Patent OwnerAddress
VALTRUS INNOVATIONS LIMITEDTHE GLASS HOUSES 92 GEORGES STREET LOWER DUN LAOGHAIRE DUBLIN A96 VR66

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hundt, Robert Palo Alto, US 45 836
Mannarswamy, Sandya S Bangalore, IN 4 89
Raman, Easwaran Princeton, US 1 22

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