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Abstract

A memory test system injects phase jitter in memory command, address and write data signals in respective pin groups. A phase interpolator receiving a clock signal is provided for each of the pin groups to generate respective delayed clock signals. The phase shift produced by each of the phase interpolators is determined by delay control values, which are passed to the phase interpolators from respective memory arrays. Each of the memory arrays stores at each address a next address along with a delay control value. The next address is used to access the memory array to obtain next delay control value. The delayed clock signals are applied to a clock input of a respective set of registers for each pin group, and a data input of each of the registers receives one of the memory device signals in the respective pin group.

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