Method and system for generating multiple implementation views of an IC design
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United States of America Patent
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Jul 27, 2010
Grant Date -
N/A
app pub date -
Jan 8, 2008
filing date -
Oct 15, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.
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