Non-volatile memory with both single and multiple level cells
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United States of America Patent
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Aug 10, 2010
Grant Date -
Apr 2, 2009
app pub date -
Dec 8, 2008
filing date -
Aug 21, 2006
priority date (Note) -
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Abstract
Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices and systems. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of single level non-volatile memory cells and a number of multiple level non-volatile memory cells, where a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell.
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