Apparatus and method for validating a computer model
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United States of America Patent
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Aug 10, 2010
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Sep 10, 2008
filing date -
May 17, 2001
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Abstract
An apparatus and method for validating a computer model is described. In one embodiment, a computer-readable medium comprises instructions to associate a set of configurations of a computer model with a stimulus-response test, each configuration of the set of configurations representing a different model scenario, the stimulus-response test defining a modification to each configuration of the set of configurations. The computer-readable medium also comprises instructions to apply the stimulus-response test to the set of configurations to produce a simulated response for each configuration of the set of configurations and instructions to compare the simulated responses for the set of configurations with an expected response to the stimulus-response test.
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