Resistive memory structure with buffer layer
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United States of America Patent
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Aug 17, 2010
Grant Date -
Jan 22, 2009
app pub date -
Jul 18, 2008
filing date -
Jul 20, 2007
priority date (Note) -
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Abstract
A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.
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