Method of generating a chaos-based pseudo-random sequence and a hardware generator of chaos-based pseudo random bit sequences
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United States of America Patent
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Aug 17, 2010
Grant Date -
Aug 5, 2004
app pub date -
Nov 12, 2003
filing date -
Nov 12, 2002
priority date (Note) -
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Abstract
summing the bits stored in the second circuit means, generating a bit of the chaos-based pseudo-random bit sequence; a second adder summing up the bit strings currently stored in the shift register and in the first circuit means, generating a bit string representing a successive number of the pseudo-random sequence.
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