Electrical parameter extraction for integrated circuit design
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United States of America Patent
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Aug 24, 2010
Grant Date -
Jul 23, 2009
app pub date -
Jan 18, 2008
filing date -
Jan 18, 2008
priority date (Note) -
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Abstract
A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.
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