Packaging chip having interconnection electrodes directly connected to plural wafers
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United States of America Patent
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Aug 31, 2010
Grant Date -
Jan 18, 2007
app pub date -
Jul 6, 2006
filing date -
Jul 15, 2005
priority date (Note) -
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Abstract
A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.
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