Programmable latch based multiplier
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United States of America Patent
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Sep 14, 2010
Grant Date -
Jul 2, 2009
app pub date -
Jan 16, 2008
filing date -
Dec 26, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.
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