Trench MOSFET and method of manufacture utilizing two masks

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7799642
APP PUB NO 20090085105A1
SERIAL NO

11866365

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Abstract

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A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
Inpower Semiconductor Co., Ltd.TAI PO NT, HK1

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Tai Chiang TianJin, CN 4 37
Lv, Long TianJin, CN 3 35
Su, Shih Tzung Shulin, TW 3 35
Sun, Poi Torrance, US 3 35
Tu, Kao Way Jhonghe, TW 4 35
Wang, Xin TianJin, CN 459 4172
Zeng, Jun Torrance, US 144 1239

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
2007/0287,275 METHOD FOR FABRICATING DOPED POLYSILICON LINES 3 2007
 
M-MOS SEMICONDUCTOR SDN. BHD. (1)
2006/0273,382 High density trench MOSFET with low gate resistance and reduced source contact space 27 2005
 
Inpower Semiconductor Co., Ltd. (3)
7687352 Trench MOSFET and method of manufacture utilizing four masks 2 2007
2009/0085,074 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING FOUR MASKS 11 2007
2009/0085,105 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING TWO MASKS 18 2007
 
INTERNATIONAL RECTIFIER CORPORATION (1)
2007/0042,552 Method for fabricating a semiconductor device 5 2006
 
ALPHA & OMEGA SEMICONDUCTOR, LTD. (1)
2002/0030,224 MOSFET POWER DEVICE MANUFACTURED WITH REDUCED NUMBER OF MASKS BY FABRICATION SIMPLIFIED PROCESSES 10 1997
 
Semiconductor Energy Laboratory Co., Ltd. (1)
5604137 Method for forming a multilayer integrated circuit 103 1995
 
ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED (1)
2006/0170,036 Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics 12 2006
 
SAMSUNG ELECTRONICS CO., LTD. (1)
2008/0233,693 COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) DEVICES INCLUDING A THIN-BODY CHANNEL AND DUAL GATE DIELECTRIC LAYERS AND METHODS OF MANUFACTURING THE SAME 7 2008
 
Advanced Analogic Technologies, Inc. (1)
2004/0191,994 Trench transistor with chained implanted body 18 2004
* Cited By Examiner

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