US Patent No: 7,804,132

Number of patents in Portfolio can not be more than 2000

Semiconductor device

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ALSO PUBLISHED AS: 20070241402
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Abstract

A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RENESAS ELECTRONICS CORPORATIONTOKYO13433

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hirano, Yuichi Tokyo, JP 11 21

Cited Art

Patent Info (Count) # Cites Year
 
GLOBALFOUNDRIES INC. (1)
6,020,222 Silicon oxide insulator (SOI) semiconductor having selectively linked body 51 1997
 
RENESAS ELECTRONICS CORPORATION (1)
2007/0176,233 Semiconductor integrated circuit 2 2006
 
TEXAS INSTRUMENTS INCORPORATED (1)
6,177,300 Memory with storage cells having SOI drive and access transistors with tied floating body connections 84 1999
 
Other [Check patent profile for assignment information] (1)
5,652,454 Semiconductor device on an SOI substrate 41 1996

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