Partial packet write and write data filtering in a multi-queue first-in first-out memory system

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United States of America Patent

PATENT NO 7805552
APP PUB NO 20060020761A1
SERIAL NO

11040896

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Abstract

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A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.

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Patent Owner(s)

  • INTEGRATED DEVICE TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Au, Mario Fremont, US 22 206
Mo, Jason Z Fremont, US 26 148
Su, Hui San Jose, US 104 1384

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