Processed wafer via

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7808111
APP PUB NO 20070197013A1
SERIAL NO

11556747

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Abstract

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An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.

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Patent Owner(s)

  • CUFER ASSET LTD. L.L.C.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Trezza, John 12 White Oak Dr. 102 2623

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