NAND flash memory devices having shielding lines between wordlines and selection lines
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United States of America Patent
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Oct 26, 2010
Grant Date -
May 28, 2009
app pub date -
Jan 22, 2009
filing date -
May 11, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines.
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