US Patent No: 7,827,226

Number of patents in Portfolio can not be more than 2000

Hybrid arithmetic logic unit

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Abstract

Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MICRON TECHNOLOGY, INC.BOISE, ID18720

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jon, Skull - 1 0

Cited Art

Patent Info (Count) # Cites Year
 
GEO SEMICONDUCTOR INC. (1)
6,167,421 Methods and apparatus for performing fast multiplication operations in bit-serial processors 2 1998
 
HITACHI, LTD. (1)
4,811,269 Bit slice multiplication circuit 39 1986
 
INTEL CORPORATION (1)
5,612,911 Circuit and method for correction of a linear address during 16-bit addressing 17 1995
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,787,492 Address limit check apparatus with conditional carry logic 7 1996
 
SIEMENS AKTIENGESELLSCHAFT (1)
4,819,198 Saturable carry-save adder 13 1986
 
SPS-AFOS INTERNATIONAL (BRANCH) LIMITED (1)
6,615,228 Selection based rounding system and method for floating point operations 3 2000
 
WISCONSIN ALUMNI RESEARCH FOUNDATION (1)
2006/0064,455 Processing unit having multioperand decimal addition 5 2004

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