Electrodes located at storage capacitor wiring in active matrix substrate
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United States of America Patent
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Nov 9, 2010
Grant Date -
Dec 18, 2008
app pub date -
Aug 18, 2008
filing date -
Jan 28, 2004
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An active matrix substrate includes a thin film transistor, a scanning signal line, and a data signal line disposed on the substrate. A gate electrode of the transistor is connected to the scanning signal line, a source electrode thereof is connected to the data signal line, and a drain electrode thereof is connected to a pixel electrode; and an upper electrode is disposed so as to oppose a storage capacitor wiring pattern at least via an insulating layer. Within a pixel region, the upper electrode includes three divided electrodes in a region opposing the storage capacitor wiring pattern, and a central divided electrode of the three divided electrodes has the smallest area.
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