System and method for optimizing interconnections of memory devices in a multichip module

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7836252
APP PUB NO 20040044833A1
SERIAL NO

10232842

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MICRON TECHNOLOGY, INC.BOISE, ID19147

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ryan, Kevin J Eagle, US 90 2237

Cited Art Landscape

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BEIJING XIAOMI MOBILE SOFTWARE CO., LTD. (1)
6718440 Memory access latency hiding with hint buffer 129 2001
 
ANPA INC. (1)
6434696 Method for quickly booting a computer system 186 1999
 
LONGITUDE SEMICONDUCTOR S.A.R.L. (4)
6201724 Semiconductor memory having improved register array access speed 137 1999
6381190 Semiconductor memory device in which use of cache can be selected 143 2000
6330205 Virtual channel synchronous dynamic random access memory 141 2000
6707726 Register without restriction of number of mounted memory devices and memory module having the same 35 2002
 
UNISYS CORPORATION (1)
5832250 Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits 139 1996
 
TALON RESEARCH, LLC (1)
6799246 Memory interface for reading/writing data from/to a memory 172 1997
 
UNIVERSITY OF SOUTHERN CALIFORNIA (1)
5568574 Modulator-based photonic chip-to-chip interconnections for dense three-dimensional multichip module integration 158 1995
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
U.S. BANK NATIONAL ASSOCIATION (1)
* 2011/0055,478 SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF MEMORY DEVICES IN A MULTICHIP MODULE 0 2010
 
MICRON TECHNOLOGY, INC. (1)
* 8190819 System and method for optimizing interconnections of memory devices in a multichip module 0 2010
* Cited By Examiner

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