System and method for protecting the contents of memory during error conditions
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United States of America Patent
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Nov 16, 2010
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N/A
app pub date -
May 15, 2007
filing date -
May 15, 2007
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Abstract
A system and method protects the contents of memory during error conditions. An illustrative storage system includes a complex programmable logic device (CPLD) that interfaces with a memory controller and a basic input output system (BIOS) for ensuring that the system memory is maintained in a self refresh state in the event of an error condition. The memory controller is configured to, in response to receiving a signal from the CPLD, cause the memory to enter the self refresh state where it is maintained by a battery subsystem (or alternate power sources). Accordingly, data contained within the memory may be replayed to persistent storage upon correction of the error condition via, for example, a system re-initialization.
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