Method and apparatus for handling failure in address line
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 14, 2010
Grant Date -
Nov 5, 2009
app pub date -
Apr 27, 2009
filing date -
Oct 27, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An address line failure handling apparatus includes a failed address line specifying unit that examines the address line connected to each bit and specifies a failed address line, an address line substituting unit in which an upper address line connected to an upper bit of the memory is connected with a branch address line branched off from a lower address line connected to a lower bit other than the upper bit, and that switches between an input from the upper address line and an input from the branch address line, and outputs any of the inputs to the upper bit, and an address line substitution instructing unit that instructs the address line substituting unit to switch from the upper address line to the branch address line branched off from the failed address line when the failed address line is specified.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully