US Patent No: 7,859,929
Number of patents in Portfolio can not be more than 2000
Sense amplifiers
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Dec 28, 2010
Issued date -
Apr 10, 2009
filing date -
12/422,152
serial no -
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Abstract
Sense logic, and associated signaling, for dynamic thyristor-based memory cells is described. A first supply voltage level is greater than a second supply voltage level. In an embodiment, cross-coupled inverters of a sense amplifier are operatively coupled between a ground node and the second supply for sensing voltage. The first supply voltage is pass gate coupled to a first sense node and a second sense node. The pass gating is responsive to sample signaling. A first supply transistor is gated by a transfer bus. A second supply transistor is gated by a sense reference voltage that is between the first supply voltage level and the second supply voltage level. Each of the first supply transistor and the second supply transistor is back body biased with a write voltage level that is between the second supply voltage level and the ground voltage level.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 6,940,772 Reference cells for TCCT based memory cells | 13 | 2002 | |
| 6,611,452 Reference cells for TCCT based memory cells | 40 | 2002 | |
| 6,785,169 Memory cell error recovery | 40 | 2002 | |
| 6,804,162 Read-modify-write memory using read-or-write banks | 20 | 2002 | |
| 6,781,888 Reference cells for TCCT based memory cells | 21 | 2002 | |
| 6,778,435 Memory architecture for TCCT-based memory cells | 15 | 2002 | |
| 6,721,220 Bit line control and sense amplification for TCCT-based memory cells | 12 | 2002 | |
| 6,958,931 Bit line control and sense amplification for TCCT-based memory cells | 15 | 2002 | |
| 6,903,987 Single data line sensing scheme for TCCT-based memory cells | 17 | 2002 | |
| 6,735,113 Circuit and method for implementing a write operation with TCCT-based memory cells | 17 | 2002 | |
| 7,187,530 Electrostatic discharge protection circuit | 8 | 2003 | |
| 6,756,838 Charge pump based voltage regulator with smart power regulation | 22 | 2003 | |
| 6,734,815 Geometric D/A converter for a delay-locked loop | 11 | 2003 | |
| 6,937,085 Sense amplifier based voltage comparator | 11 | 2003 | |
| 6,891,774 Delay line and output clock generator using same | 17 | 2003 | |
| 6,947,349 Apparatus and method for producing an output clock pulse and output clock generator using same | 11 | 2003 | |
| 7,089,439 Architecture and method for output clock generation on a high speed memory device | 6 | 2003 | |
| 7,464,282 Apparatus and method for producing dummy data and output clock generator using same | 4 | 2003 | |
| 6,885,581 Dynamic data restore in thyristor-based memory device | 39 | 2003 | |
| 6,944,051 Data restore in thryistor based memory devices | 18 | 2003 | |
| 7,304,327 Thyristor circuit and approach for temperature stability | 7 | 2003 | |
| 7,054,191 Method and system for writing data to memory cells | 5 | 2004 | |
| 7,096,144 Digital signal sampler | 6 | 2004 | |
| 7,268,373 Thyristor-based memory and its method of operation | 9 | 2004 | |
| 7,573,077 Thyristor-based semiconductor memory device with back-gate bias | 7 | 2005 | |
| 7,460,395 Thyristor-based semiconductor memory and memory array with data refresh | 7 | 2005 | |
| 7,319,622 Bitline shielding for thyristor-based memory | 5 | 2005 | |
| 7,379,381 State maintenance pulsing for a memory device | 4 | 2005 | |
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| 6,201,418 Differential sense amplifier with reduced hold time | 15 | 1998 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
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| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Jun 28, 2014 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jun 28, 2018 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jun 28, 2022 |
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