System and method for enhanced error detection in memory peripherals
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United States of America Patent
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Jan 4, 2011
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N/A
app pub date -
Dec 7, 2005
filing date -
Dec 8, 2004
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Abstract
A system and method for detecting and correcting errors in a memory in a device includes generating an error value of data stored at first predetermined locations in a first memory. The generated error value is compared to a corresponding error value stored in an error memory, each value in the error memory being calculated from at least two data values stored at predetermined locations in the first memory. The data stored in the first predetermined locations of the first memory is rewritten with data stored in first predetermined locations of a second memory if the generated error value is different than the corresponding error value stored in the error memory, the data stored in the second memory being the same as the data stored in the first memory.
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