System and method for performing transistor-level static performance analysis using cell-level static analysis tools
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United States of America Patent
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Jan 4, 2011
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Mar 12, 2008
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Mar 12, 2007
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Abstract
A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static performance analysis on a circuit represented by a transistor level netlist. The method begins with converting said transistor-level netlist to a cell-level netlist by modeling individual transistors with a cell model. Then, a static performance analyzer is used to perform a static performance analysis of said cell-level netlist. Among performance characteristics that may be analyzed are timing (static timing analysis) and leakage power. The method described may also be used for statistical static timing and power analysis.
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