Low stress cavity package

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7868433
SERIAL NO

12202112

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Abstract

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The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL SEMICONDUCTOR CORPORATIONBATU BERENDAM FREE TRADE ZONE MELAKA 75350

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
How, You Chye Melaka, MY 29 183
Lim, Peng Soon Melaka, MY 12 129
Yeong, Shee Min Melaka, MY 8 110

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