Transitioning to and from a sleep state of a processor
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United States of America Patent
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Jan 11, 2011
Issued Date -
N/A
app pub date -
Aug 21, 2007
filing date -
Oct 23, 2000
priority date (Note) -
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Abstract
A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
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