Importance

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Abstract

A semiconductor integrated circuit includes a plurality of clock gating circuits, a plurality of flip-flops to which transmission of a clock signal is controlled by a respective clock gating circuit, and a clock gating control circuit that controls an active state and an inactive state of the plurality of clock gating circuits, wherein during a test operation mode, the clock gating control circuit controlling the active state and the inactive state of the plurality of clock gating circuits according to a user logic signal, and controlling setting of an arbitrary combination of clock gating circuits to an inactive state regardless of the user logic signal.

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First Claim