LDMOS device with multiple gate insulating members
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United States of America Patent
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Jan 25, 2011
Issued Date -
N/A
app pub date -
Dec 1, 2008
filing date -
Jul 22, 2004
priority date (Note) -
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Abstract
An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.
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