Tri-core architecture for reducing MAC layer processing latency in base stations
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United States of America Patent
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Feb 1, 2011
Grant Date -
Dec 31, 2009
app pub date -
Jun 22, 2009
filing date -
Jun 30, 2008
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Abstract
A tri-core architecture for reducing MAC layer processing latency at the base stations is described. The new architecture minimizes the processing delay by introducing a pipelined approach. The fundamental concept involves splitting the Medium Access Control (MAC) layer functionality into three distinct tasks, with each processor performing a given task. All tasks will be thus performed concurrently, avoiding much of the overhead encountered while processing received packets and preparing packets to be transmitted.
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