Method of extending default fixed number of processing cycles in pipelined packet processor architecture
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United States of America Patent
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Feb 15, 2011
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N/A
app pub date -
Dec 30, 2005
filing date -
Apr 28, 2004
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Abstract
In a packet processing system, where a packet processor normally performs a fixed number of processing cycles on a packet as it progresses through a processing pipeline, a method of extending the fixed number of processing cycles for a particular packet is provided. During the processing of a packet, an extension bit associated with the packet is set to an “on” state if extended processing of the packet is needed. While the extension bit is set to that state, updating of a count, indicating the number of processing cycles that has been undertaken for the packet, is inhibited. When the extended processing of the packet has been completed, the extension bit for the packet is set to an “off” state, and the updating of the count resumed. When that count indicates the number of processing cycles the packet has undergone equals or exceeds the fixed number, the packet is exited from the pipeline.
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