For testability technique for phase detectors used in digital feedback delay locked loops
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United States of America Patent
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Feb 22, 2011
Grant Date -
Feb 25, 2010
app pub date -
Oct 27, 2009
filing date -
Nov 30, 2007
priority date (Note) -
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Abstract
A circuit for testing phase detectors in a delay locked loop is provided. The circuit uses a second phase detector arranged to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.
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