I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 1, 2011
Issued Date -
N/A
app pub date -
Dec 3, 2009
filing date -
Dec 20, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully