Systems and methods for monitoring and controlling binary state devices using a memory device
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United States of America Patent
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Mar 8, 2011
Grant Date -
Dec 7, 2006
app pub date -
Aug 10, 2006
filing date -
Nov 17, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
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